In the second embodiment, in a manner similar to the first embodiment, the delay of the CMOS LSI can be compensated and the threshold voltage difference between the PMOS transistor and the NMOS transistor can be eliminated. In addition, by feeding back the signal vbap to the PN Vt balance compensation circuit 123, even if the threshold voltage difference occurs between the PMOS transistor and the NMOS transistor at the time of changing the signals vbap and vban in order to compensate delay, the difference can be compensated.